The company appears well positioned to challenge CPU incumbents with high performance RISC-V CPUs and Vector Extensions to the open ISA architecture. The RISC-V CPU Instruction Set Architecture (ISA) ...

The computing industry has reached a significant milestone with the ratification of the 1.0 RISC-V Vector Specification. This development marks the beginning of a new era in computing efficiency, as ...

Though the RISC-V Summit North America is over, you can peruse the videos of most of the keynotes and sessions here. The list is quite long, so we picked a few and included them in this space, such as ...

Many have waited years to hear someone like Prahlad Venkatapuram, Senior Director of Engineering at Meta, say what came out this week at the RISC-V Summit: “We’ve identified that RISC-V is the way to ...

A search is underway across the industry to find the best way to speed up machine learning applications, and optimizing hardware for vector instructions is gaining traction as a key element in that ...

The technology driving our world today is increasingly complex. From the latest flashy AI technology like ChatGPT to autonomous cars and satellite launches to the innovations behind our everyday ...

RISC-V cores are beginning to show up in heterogeneous SoCs and packages, shifting from one-off standalone designs toward mainstream applications where they are used for everything from accelerators ...

Why Synopsys’ entry into the RISC-V field is significant. What RISC-V families are supported by Synopsys. Synopsys just released its ARC-V family of RISC-V-based processors (see figure). Those ...

We’ve heard the story before. I was a proponent of it in the late 1990s, with the ‘first fully configurable’ processor core. So, did we already experience the ‘first’ one many years ago, or was the ...