SAN FRANCISCO — Stanley Hyduke sees a not-so-distant future for the semiconductor industry in which companies are running thousands of simultaneous simulations to cope with the verification bottleneck ...
Riviera-SNA is a batch mode, common kernel, and multi-language simulator. Based on Aldec’s VHDL and Verilog mixed-language simulation technology, the product supports large verification teams seeking ...
Some results have been hidden because they may be inaccessible to you
Show inaccessible results